1. Field of the Invention
The invention relates to shadow masking processes in microelectronic fabrication, particularly those employed in silicon-on-sapphire (SOS) processes.
2. Description of the Prior Art
The fabrication of integrated circuits such as metal oxide semiconductor (MOS) circuits employing a mask and photolithographic techniques is well known in the art. One of these methods, known as the self-aligned gate procedure, utilizes a gate conductor pattern to shield the channel region of the device from N+ or P+ ion implantation during formation of the source and drains of the device. In such processes, the entire dimension of the gate, L, shields the channel region which has an area L by W (wherein W is within the channel region) from the N+ or P+ ion implantation due to the thickness of the gate conductor. The source and drain regions of the device fabricated according to such a self-aligned gate process are not appreciably overlapped by the gate and therefore the Miller capacitance of the device is minimized.
Although such a procedure is adequate for many standard commercial products, when the channel of the device is reduced to submicrometer dimensions, such as VLSI or highly integrated devices, the depletion layers in the source and drain regions overlap to a certain extent depending upon the doping concentration distribution of the channel region of the device. It should be noted that in the enhancement mode, depletion mode, or deep depletion mode of operation of the device, the channel region will be bounded by a vertical N+ and P+ region for the source and drain down to at least a distance of 0.25 micrometers from the silicon/silicon dioxide interface and usually through the entire Si film to the sapphire. This bound is due to the vertical slope of the etches of the gate conductor. Immediately below the channel region, the depletion layers overlap more and punchthrough is enhanced. Punchthrough is symptomized by a drain-source voltage dependence of the subthreshold current. It is also known as a short channel effect.
One approach to a channel making process for forming the source and drain regions as a MOS device is shown in U.S. Pat. No. 4,198,250, which utilizes a gate masking member which is etched and the gate oxide beneath the gate undercut to form overhangs. When a substrate is subjected to ion implantation with such a mask, a much shallower concentration of impurities is implanted in the substrate beneath the overhangs than in the substrate region not protected by the masking member. Such a process provides self alignment for the gate and the source and drain regions will be overlapped by the gate more than with the plain self-aligned gate process. The Miller capacitance will be increased slightly compared to the usual S.A.G. (Self-Aligned Gates) process, but, the likelihood for punchthrough is reduced.
The disadvantage of the process described in the above noted patent is that the amount of undercut for submicrometer gate dimensions is uncontrollable. The prior art describes a process for 2-4 .mu.m gate lengths where the undercut is typically 0.25 to 0.5 .mu.m on each side. However, it is obvious that any undercut of a 0.5 .mu.m gate length will be too significant, e.g., only 300 Angstroms on a side undercut is 12% and is not uniform from wafer to wafer and on an individual wafer because of the isotropic etches required by the prior art.